High-Speed and Low-Power Embedded TEC BCH Scheme for ReRAM Array

This paper proposes an embedded TEC BCH scheme for ReRAM array, which is capable of low access time and uniform error distribution. The high speed decoder with SBSA proposed a fully-parallel architecture. An optimized adaptive correction approach utilized to reduce the power consumption. Furthermore, composite field arithmetic used minimize logical size. For performance evaluation, implemented on Xilinx Virtex-7 FPGA, synthesized 65nm CMOS technology, can achieve 62.72 Gb/s throughput at decoding frequency 490MHz 0.95ns delay 774.1